DISCLAIMER: THE TEXT INCLUDED IN THIS POST ARE FROM SOLID STATE PULSE CIRCUITS BY DAVID BELL PP 380-384. SITE THE AUTHOR IF YOU WILL USE IT. THIS POST IS FOR OUR GROUP REPORT ONLY AND NO OTHER PERSONAL INTEREST IS INVOLVED. THE IMAGES WERE COPIED FROM THE SAME BOOK BUT WERE CREATED BY ME THROUGH DIFFERENT CAPTURE AND SCHEMATICS APPLICATION SOFTWARE. ASK PERMISSION FIRST IF YOU WILL GRAB ANYTHING. MARAMING SALAMAT PO!

12-4 OPEN-COLLECTOR TTL

An open-collector TTL logic gate has an output stage which consists of a single transistor with its collector terminal unconnected. [See Figure 12-8(a).] The complete gate circuit is similar to that in Figure 12-7, with components Q3, R4, and D4 omitted. An external pull-up resistor Rc must be included, as illustrated in Figure 12-8(a), to provide a path for the transistor collector current.

Figure 12-8 Open-collector TTL gates have transistors with open-circuited collector terminals as their output stages. This permits gate output terminals to be connected together to function as an AND gate.

Figure 12-8(b) shows that a single collector resistor can serve the outputs of several open-collector gates. The gate outputs are connected together in an arrangement termed wired-AND configuration. Because each gate has an open-collector output, it is not loaded by the other gates. (This would not be the case with totem pole output stages.) If the output of any one gate is low, the wired-AND output is low. The wired-AND output is high only when a high level is present at terminal A and at terminal B and at terminal C. [See Figure 12-8(b).] It is seen that this wiring arrangement functions as an AND gate, hence the name wired-AND arrangement available with open-collector TTL is that it can be substituted in place of a logic gate. Consider the digital comparator circuit in Figure 11-19. The AND gate can be eliminated if open-collector TTL XNOR gates are available.

12-5 TRI-STATE TTL (TSL)

A tri-state TTL (or TSL) logic gate has a control input as well as the usual input and output terminals. Figure 12-9 shows the circuit arrangement and logic symbol for a TSL NAND gate. Note that the control input terminal goes to an inverter. The output of the inverter is connected to one emitter on transistor Q1 and to the base of Q3 via diode D1.

When the control input is low, the inverter output is high. This reverse biases D1 and provides a high input to the connected emitter Q1. In this condition the NAND gate functions normally; when all the gate inputs are high, the output is low; when one or more inputs are low, the output is high.

Figure 12-9 Tri-ste TTL (TSL) circuits have a third output state: in addition to being high or low, the output may be placed in a high-impedance state. This is accomplished by setting transistors Q3 and Q4 in an off condition.

When a high input applied to the control terminal, the inverter output goes low, forward-biasing D1 and the connected emitter of Q1. Now Q1 is held in a low state, regardless of the level of the other gate input terminals. Thus, Q2 and Q4 are off. In addition, the base of Q3 is held in a low state by (forward-biased) diode D1. Consequently, Q3 is off. Both output transistors Q3 and Q4 are off, and the output terminal offers a high impedance to all circuits that are connected to it. This condition is the third state of the TSL circuit: the output of a TSL gate may be high or low, or have a high output impedance.

TSL gates are used in logic systems where the outputs of several gates are connected in parallel to a single input of another circuit. All gates are usually maintained in the high output impedance state and are sampled, or switched on briefly one at a time, by the control signals applied in sequence. This avoids the possibility of the output of one gate short-circuiting another gate output.

Another aspect of the TSL gate is that the circuit input impedance also becomes high when the gate is placed in its high output impedance state.

High-Speed TTL (54H/74H)

The circuit speed is increased by reducing the resistance of the resistors and by including an additional emitter-follower transistor to drive one of the output transistors. (See the H00-H30 circuit diagram in the data sheet.) Because of the reduced resistor values, the supply current is approximately double that for standard TTL, resulting in an average per-gate power dissipation of 22.5 mW. The typical propagation delay time for 54H/74H TTL is 6ns.

Schottky TTL (54S/74S)

This logic family employs Schottky transistors to further increase the circuit switching speed. A Schottky transistor is a bipolar transistor with a Schottky diode connected between its collector and base terminals, as illustrated in Figure 12-10(a). A Schottky diode has a junction of silicon and metal. Like other diodes, it is a one-way device, but its major characteristics are that it switches very fast and that its forward drop is typically 0.25 V. The presence of the Schottky diode prevents the transistor from going into saturation, and consequently the transistor switching speed is minimized.

The Schottky transistor circuit symbol is illustrated in Figure 12-10(b), and an S00-S133 Schotkky TTl NAND gate circuit is shown in the data sheet in Appendix 1-18.

The typical propagation delay time for Schottky TTL is 3ns, and the average power dissipation per gate is around 20mW. An improved version known as advanced Schottky TTL (54/74 AS) boasts a 1.5 ns typical gate delay tie, with 20 mW per gate power dissipation. Obviously, this type of logic circuit should be used where high speed is the most important consideration.

Figure 12-10 A Schottky transistor is a bipolar transistor with a Schottky diode connected from base to collector. This prevents the transistor from saturating, and thus increases its switching speed.

Go to my Multiply to check the variety show pictures care of Candice and Su! Thanks gals!

This morning i received a text message from GlobeRewards telling me that I received 15 free text messages. Later at noontime I received another text from Globe but now it is from 2870. I received a confirmation message that I can now use Unlitxt but I did not avail anything. Free txt and free unli. Yei :))

I thought failure was not an option, it was. Guys, we failed because I failed you. To all those who gave their best and did not had a moment because "something came up", I am sorry :C Really, really sorry because I saw everybody's effort. That is all I can say for now. It was depressing.

Sa lahat ng kinauukulan basahin ito ng dahan-dahan.

Ang tema ng ating variety show ay:

"The Singing Deal: Bee or no Bee"

Host: Buboy - Arvin B.
Kris Yap - Suzanne G.

Ang tema ng laro ay ganito, may anim na manlalaro na mamimili ng briefcases. Ang nilalaman ng briefcases ay ang mga kanta na hindi alam ng mga contestant. May anim na contestant at anim na hahawak ng briefcases. Katulad din ito ng original to bee continued round ng Singing Bee ngunit nilagyan ng kalokohan.

Ang mga contestant ay mga karakter ng Primetime Bida at GMA Telebabad shows ngunit mga minor roles lamang ito.

May 2 ng contestant tayong nahagilap. Kailangan pa natin ng 4, kayo na din ang magbigay ng minor character na gusto niyong gampanan.

*Pip-Silva ng Lobo
*Gab-Nikolas ng Betty la Fea
*
*
*
*

Kailangan ng 6 na hahawak ng briefcases. Ito na ang mga karakter na gagampanan. Mamili na lang kayo.

*Dyosa
*Dyesebel
*Mike Enriquez
*Mel Tiangco
*Julius Babao
*Ces Drilon w/ 2 Abu Sayyaf

2 ang papasok sa Manuhan Round. Ang magiging tema nito ay ganito. Magbibigay ng year ang host at mag-uunahan sa pagbuzzer ang 2 contestant kung play or pass. Dapat kantahin ng player ang susunond na apat na linya upang manalo.

Lumalabas na kailangan ng pitong [7] kanta lahat-lahat.

Ang mananalo ay papasok sa jackpot round na tatawaging Bee or No Bee!

Ganito naman ang tema ng Bee or No Bee!

Ang mananalo ay may pagpipilian na 8 briefcase na hahawakan ng mga karakter na sila: (mamili na lang kayo dahil yung iba wala pang tao)

*Darna with Ding -
*Palos - Rap
*Asero - Arvin I.
*Kim Sam Soon -
*My Girl -
*Kamandag - Renz
*Bordado - Boy
*Dyosabel or Dyesebol ang fusion ni Dyosa at Dyesebel -

Kailangan din ng kapamilya ng player na mananalo: dapat madalas humirit itong mga to at nakikialam sa player sa mga pipiliin nitong briefcases.

*Mother -
*Father -
*Kapatid -
*Kapatid -
*Kapatid or Lolo or Lola-
*Lolo or Lola -

Kailangan din ng mga singers na kakanta apat ang kailangan 3 pa lang ang meron:

*Paolo
*Mika
*Dudes
*

Kailangan din ng dancers for both show na ito. Kailangan sumali ang host sa sayawan. Isip na lang ng choreo.

*Host
*Host
*Dudes
*
*
*
*
*

Kailangan din mag-isip ng action para sa "The Singing Deal" at action para sa "Bee or No Bee!"
Pwede pang mapalitan ang konseptong ito at ayos na ayos kung kayo ay magbibigay ng mga magagandang reaksiyon o komento. pwede ring gumanap ng higit sa isa kung inyong kakayanin. pwede rin palitan ang mga karakter na nabanggit na kung saan kayo komportableng gumanap o komprotable niyong gayahin. maraming salamat! magcomment na lamang kayo dito!

As what was "co-proposed" by Jarome Lopez and Emman Inieto, we are going to use our black jersey instead of our blue jersey on our remaining games in our NECES tourney. Please be noted about this. Thanksü

Nights are getting longer than days and cool breeze in the evening is felt. One thing is in our hearts and minds. The Yuletide Season! It is the time to be merry and jolly. Hahaha. Merry Christmas to all!

It was a good idea to make the anticipated Pacquiao-Dela Hoya fight be happened on a very important day in our lives. December 7. My birthday! Happy Birthday to me. Maybe an important day in my life only.

By the way, my Multiply account is active right now. Click Here! to direct to the portal.